View SD1210_4305015.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

smartasic, inc. sd1 2 10 november , 1999 smartasic confidential 1 revision b data sheet sd1 2 10 dual -interface s xga tft lcd display controller november 1999
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 2 revision b sd1 2 10 data sheet dat- sd1 2 10 - 1 1 99 - b november 1999 document revisions date dat- sd1 2 10 - 1099 -a sd1 2 10 data sheet - a october 1999 dat-sd1 2 10-1199-b sd1 2 10 data sheet - b november 1999 copyright 1999, smartasic, inc. all right reserved smartasic, inc. reserves the right to change or modify the information contained herein without notice. it is the customer?s responsibility to ensure he/she has the most recent revision of the user guide. smartasic, inc. makes no warranty for the use of its products and bears no responsibility for any error or omissions, which may appear in this document.
smartasic, inc. sd1 2 10 november , 1999 smartasic confidential 3 revision b 1. overview the sd1 2 10 is enhanced version of the sd1 2 00 chip. it is an ic designed for dual - interface s xga tft lcd monitors. a dual -interface lcd monitor takes analog or digital rgb signals from a graphic card of a personal computer, the exact same input interface as a conventional crt monitor. this feature makes a dual -interface lcd monitor a true replacement for a conventional crt monitor. the analog input rgb signals are first sampled by six channels of 8-bit a/d converters, and the 48-bit rgb data are then fed into the sd1 2 10 . for digital interface, the input data are first received by a tmds receiver, and the 24/48 bit rgb output data of tmds receiver are then fed into the sd1 2 10. the sd1 2 10 is capable of performing automatic detection of the display resolution and timing of input signals generated from various pc graphic cards. no special driver is required for the timing detection, nor any manual adjustment. the sd1 2 10 then automatically scales the input image to fill the full screen of the lcd monitor. the sd1 2 10 can interface with tft lcd panels from various manufacturers by generating either 24-bit or 48-bit rgb signal to the lcd panel based upon the timing parameters saved in the eeprom. the sd1 2 10 implements four advanced display technologies: 1. advanced mode detection and auto-calibration without any external cpu assist 2. advanced programmable interpolation algorithm 3. stand-alone mode support, and 4. advanced true color support with both dithering and frame modulation. the sd1 2 10 also provides distinguished system features to the tft lcd monitor solution. the first one is ?plug-and-play?, and the second one is ?cost-effective system solution?. to be truly plug-and-display, the sd1 2 10 performs automatic input mode detection and auto phase calibration, so the lcd monitor can ensure that the a/d converters? sample clock is precisely synchronized with the input video data, and to preserve the highest image bandwidth for the highest image quality. furthermore, the sd1 2 10 can generate output video even when the input signal is beyond the specifications or no input signal is fed. for ?cost-effective system solution?, the sd1 2 10 implements many system support features such as osd mixer, error status indicators, 2-wire serial interface for both eeprom and host cpu interface, and low-cost ic package. another important contributing factor is that the sd1 2 10 does not require external frame buffer memory for the automatic image scaling and synchronization. figure 1 shows the block diagram of the sd1 2 10 as well as the connections of important system components around the sd1 2 10 .
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 4 revision b figure 1: sd1 2 10 functional block diagram input mode detection & auto calibration buffer memory scaling interpolation dithering osd mixer write control read control cpu interface e 2 rom interface adc phase control input pll cpu output pll e 2 prom tft lcd monitor
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 5 revision b 2. pin description figure 2: sd1 2 10 package diagram smartasic sd1 2 10 1 40 41 80 120 81 160 121
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 6 revision b table 1: sd1 2 10 pin description (sorted by pin number) symbol pin number i/o description b_in10 1 i channel b data input color blue (lsb) b_in11 2 i channel b data input color blue b_in12 3 i channel b data input color blue b_in13 4 i channel b data input color blue data_sel 5 i indicate channel a or channel b contains valid input data: 1: data in channel a is valid 0: data in channel b is valid b_in14 6 i channel b data input color blue b_in15 7 i channel b data input color blue b_in16 8 i channel b data input color blue b_in17 9 i channel b data input color blue (msb) rom_scl 10 o scl in i 2 c for eeprom interface rom_sda 11 i/o sda in i 2 c for eeprom interface gnd 12 ground cpu_scl 13 i scl in i 2 c for cpu interface cpu_sda 14 i/o sda in i 2 c for cpu interface pwm_ctl 15 o pwm control signal (detail description in pwm operation section) clk_1m 16 i free running clock (default: 1mhz) vdd 17 power supply clk_1m_o 18 o feedback of free running clock reset_b 19 i system reset ( active low) r_osd 20 i osd color red g_osd 21 i osd color green b_osd 22 i osd color blue en_osd 23 i osd mixer enable =0, no osd output =1,r_out[7:0]= {r_osd repeat 8 times} g_out[7:0]= {g_osd repeat 8 times } b_out[7:0]= {b_osd repeat 8 times } scan_en 24 i manufacturing test pin (nc) test_en 25 i manufacturing test pin (nc) vclk01 26 i input clock 1 fclk0 27 o input pll feedback clock vclk00 28 i input clock 0 fclk1 29 o output pll feedback clock vclk1 30 i output pll output clock hsync_o 31 o output hsync (the polarity is programmable through cpu, default is active low) vsync_o 32 o output vsync (the polarity is programmable through cpu, default is active low) dclk_out 33 o output clock to control panel (the polarity is programmable through cpu) de_out 34 o output display enable for panel (the polarity is programmable through cpu, default is active high) gnd 35 ground vdd 36 power supply r_out0_e 37 o output color red even pixel (left pixel)
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 7 revision b r_out1_e 38 o output color red even pixel (left pixel) r_out2_e 39 o output color red even pixel (left pixel) r_out3_e 40 o output color red even pixel (left pixel) hsync_x 41 o default hsync generated by asic (active low) vsync_x 42 o default vsync generated by asic (active low) gnd 43 ground r_out4_e 44 o output color red even pixel (left pixel) vdd 45 power supply vdd 46 power supply r_out5_e 47 o output color red even pixel (left pixel) gnd 48 ground r_out6_e 49 o output color red even pixel (left pixel) r_out7_e 50 o output color red even pixel (left pixel) gnd 51 ground r_out0_o 52 o output color red odd pixel (right pixel) r_out1_o 53 o output color red odd pixel (right pixel) r_out2_o 54 o output color red odd pixel (right pixel) r_out3_o 55 o output color red odd pixel (right pixel) vdd 56 power supply r_out4_o 57 o output color red odd pixel (right pixel) r_out5_o 58 o output color red odd pixel (right pixel) r_out6_o 59 o output color red odd pixel (right pixel) r_out7_o 60 o output color red odd pixel (right pixel) gnd 61 ground g_out0_e 62 o output color green even pixel (left pixel) g_out1_e 63 o output color green even pixel (left pixel) g_out2_e 64 o output color green even pixel (left pixel) g_out3_e 65 o output color green even pixel (left pixel) g_out4_e 66 o output color green even pixel (left pixel) vdd 67 power supply g_out5_e 68 o output color green even pixel (left pixel) g_out6_e 69 o output color green even pixel (left pixel) g_out7_e 70 o output color green even pixel (left pixel) gnd 71 ground gnd 72 ground g_out0_o 73 o output color green odd pixel (right pixel) g_out1_o 74 o output color green odd pixel (right pixel) g_out2_o 75 o output color green odd pixel (right pixel) g_out3_o 76 o output color green odd pixel (right pixel) vdd 77 power supply g_out4_o 78 o output color green odd pixel (right pixel) g_out5_o 79 o output color green odd pixel (right pixel) g_out6_o 80 o output color green odd pixel (right pixel) g_out7_o 81 o output color green odd pixel (right pixel) gnd 82 ground gnd 83 ground b_out0_e 84 o output color blue even pixel (left pixel) b_out1_e 85 o output color blue even pixel (left pixel) b_out2_e 86 o output color blue even pixel (left pixel) b_out3_e 87 o output color blue even pixel (left pixel) b_out4_e 88 o output color blue even pixel (left pixel) b_out5_e 89 o output color blue even pixel (left pixel)
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 8 revision b b_out6_e 90 o output color blue even pixel (left pixel) vdd 91 power supply vdd 92 power supply b_out7_e 93 o output color blue even pixel (left pixel) gnd 94 ground b_out0_o 95 o output color blue odd pixel (right pixel) b_out1_o 96 o output color blue odd pixel (right pixel) b_out2_o 97 o output color blue odd pixel (right pixel) b_out3_o 98 o output color blue odd pixel (right pixel) vdd 99 power supply b_out4_o 100 o output color blue odd pixel (right pixel) b_out5_o 101 o output color blue odd pixel (right pixel) b_out6_o 102 o output color blue odd pixel (right pixel) b_out7_o 103 o output color blue odd pixel (right pixel) gnd 104 ground r_in00 105 i channel a data input color red (lsb) r_in01 106 i channel a data input color red r_in02 107 i channel a data input color red r_in03 108 i channel a data input color red vdd 109 power supply r_in04 110 i channel a data input color red r_in05 111 i channel a data input color red r_in06 112 i channel a data input color red r_in07 113 i channel a data input color red (msb) r_in10 114 i channel b data input color red (lsb) r_in11 115 i channel b data input color red gnd 116 ground r_in12 117 i channel b data input color red r_in13 118 i channel b data input color red vdd 119 power supply r_in14 120 i channel b data input color red r_in15 121 i channel b data input color red r_in16 122 i channel b data input color red r_in17 123 i channel b data input color red (msb) gnd 124 ground g_in00 125 i channel a data input color green (lsb) g_in01 126 i channel a data input color green g_in02 127 i channel a data input color green g_in03 128 i channel a data input color green vdd 129 power supply g_in04 130 i channel a data input color green g_in05 131 i channel a data input color green adc_clk0 132 o sample clock for adc 0 g_in06 133 i channel a data input color green g_in07 134 i channel a data input color green (msb) gnd 135 ground g_in10 136 i channel b data input color green (lsb) g_in11 137 i channel b data input color green adc_clk1 138 o sample clock for adc 1 g_in12 139 i channel b data input color green g_in13 140 i channel b data input color green vdd 141 power supply
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 9 revision b g_in14 142 i channel b data input color green g_in15 143 i channel b data input color green g_in16 144 i channel b data input color green g_in17 145 i channel b data input color green (msb) gnd 146 ground b_in00 147 i channel a data input color blue (lsb) b_in01 148 i channel a data input color blue b_in02 149 i channel a data input color blue vdd 150 power supply b_in03 151 i channel a data input color blue b_in04 152 i channel a data input color blue b_in05 153 i channel a data input color blue b_in06 154 i channel a data input color blue b_in07 155 i channel a data input color blue (msb) gnd 156 ground hsync_i 157 i input hsync (any polarity) vsync_i 158 i input vsync (any polarity) de_in 159 i de input for digital interface vdd 160 power supply
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 10 revision b table 2: sd1 2 10 pin description (sorted by function) symbol pin number i/o description r_in00 105 i channel a data input color red (lsb) r_in01 106 i channel a data input color red r_in02 107 i channel a data input color red r_in03 108 i channel a data input color red r_in04 110 i channel a data input color red r_in05 111 i channel a data input color red r_in06 112 i channel a data input color red r_in07 113 i channel a data input color red (msb) r_in10 114 i channel b data input color red (lsb) r_in11 115 i channel b data input color red r_in12 117 i channel b data input color red r_in13 118 i channel b data input color red r_in14 120 i channel b data input color red r_in15 121 i channel b data input color red r_in16 122 i channel b data input color red r_in17 123 i channel b data input color red (msb) g_in00 125 i channel a data input color green (lsb) g_in01 126 i channel a data input color green g_in02 127 i channel a data input color green g_in03 128 i channel a data input color green g_in04 130 i channel a data input color green g_in05 131 i channel a data input color green g_in06 133 i channel a data input color green g_in07 134 i channel a data input color green (msb) g_in10 136 i channel b data input color green (lsb) g_in11 137 i channel b data input color green g_in12 139 i channel b data input color green g_in13 140 i channel b data input color green g_in14 142 i channel b data input color green g_in15 143 i channel b data input color green g_in16 144 i channel b data input color green g_in17 145 i channel b data input color green (msb) b_in00 147 i channel a data input color blue (lsb) b_in01 148 i channel a data input color blue b_in02 149 i channel a data input color blue b_in03 151 i channel a data input color blue b_in04 152 i channel a data input color blue b_in05 153 i channel a data input color blue b_in06 154 i channel a data input color blue b_in07 155 i channel a data input color blue (msb) b_in10 1 i channel b data input color blue (lsb) b_in11 2 i channel b data input color blue b_in12 3 i channel b data input color blue b_in13 4 i channel b data input color blue b_in14 6 i channel b data input color blue b_in15 7 i channel b data input color blue b_in16 8 i channel b data input color blue b_in17 9 i channel b data input color blue (msb)
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 11 revision b data_sel 5 i indicate channel a or channel b contains valid input data: 1: data in channel a is valid 0: data in channel b is valid hsync_i 157 i input hsync (any polarity) vsync_i 158 i input vsync (any polarity) de_in 159 i de input for digital interface adc_clk0 132 o sample clock for adc 0 adc_clk1 138 o sample clock for adc 1 r_out0_e 37 o output color red even pixel (left pixel) r_out1_e 38 o output color red even pixel (left pixel) r_out2_e 39 o output color red even pixel (left pixel) r_out3_e 40 o output color red even pixel (left pixel) r_out4_e 44 o output color red even pixel (left pixel) r_out5_e 47 o output color red even pixel (left pixel) r_out6_e 49 o output color red even pixel (left pixel) r_out7_e 50 o output color red even pixel (left pixel) r_out0_o 52 o output color red odd pixel (right pixel) r_out1_o 53 o output color red odd pixel (right pixel) r_out2_o 54 o output color red odd pixel (right pixel) r_out3_o 55 o output color red odd pixel (right pixel) r_out4_o 57 o output color red odd pixel (right pixel) r_out5_o 58 o output color red odd pixel (right pixel) r_out6_o 59 o output color red odd pixel (right pixel) r_out7_o 60 o output color red odd pixel (right pixel) g_out0_e 62 o output color green even pixel (left pixel) g_out1_e 63 o output color green even pixel (left pixel) g_out2_e 64 o output color green even pixel (left pixel) g_out3_e 65 o output color green even pixel (left pixel) g_out4_e 66 o output color green even pixel (left pixel) g_out5_e 68 o output color green even pixel (left pixel) g_out6_e 69 o output color green even pixel (left pixel) g_out7_e 70 o output color green even pixel (left pixel) g_out0_o 73 o output color green odd pixel (right pixel) g_out1_o 74 o output color green odd pixel (right pixel) g_out2_o 75 o output color green odd pixel (right pixel) g_out3_o 76 o output color green odd pixel (right pixel) g_out4_o 78 o output color green odd pixel (right pixel) g_out5_o 79 o output color green odd pixel (right pixel) g_out6_o 80 o output color green odd pixel (right pixel) g_out7_o 81 o output color green odd pixel (right pixel) b_out0_e 84 o output color blue even pixel (left pixel) b_out1_e 85 o output color blue even pixel (left pixel) b_out2_e 86 o output color blue even pixel (left pixel) b_out3_e 87 o output color blue even pixel (left pixel) b_out4_e 88 o output color blue even pixel (left pixel)
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 12 revision b b_out5_e 89 o output color blue even pixel (left pixel) b_out6_e 90 o output color blue even pixel (left pixel) b_out7_e 93 o output color blue even pixel (left pixel) b_out0_o 95 o output color blue odd pixel (right pixel) b_out1_o 96 o output color blue odd pixel (right pixel) b_out2_o 97 o output color blue odd pixel (right pixel) b_out3_o 98 o output color blue odd pixel (right pixel) b_out4_o 100 o output color blue odd pixel (right pixel) b_out5_o 101 o output color blue odd pixel (right pixel) b_out6_o 102 o output color blue odd pixel (right pixel) b_out7_o 103 o output color blue odd pixel (right pixel) hsync_o 31 o output hsync (the polarity is programmable through cpu, default is active low) vsync_o 32 o output vsync (the polarity is programmable through cpu, default is active low) dclk_out 33 o output clock to control panel (the polarity is programmable through cpu) de_out 34 o output display enable for panel (the polarity is programmable through cpu, default is active high) vclk01 26 i input clock 1 fclk0 27 o input pll feedback clock vclk00 28 i input clock 0 fclk1 29 o output pll feedback clock vclk1 30 i output pll output clock rom_scl 10 o scl in i 2 c for eeprom interface rom_sda 11 i/o sda in i 2 c for eeprom interface cpu_scl 13 i scl in i 2 c for cpu interface cpu_sda 14 i/o sda in i 2 c for cpu interface pwm_ctl 15 o pwm control signal (detail description in pwm operation section) clk_1m 16 i free running clock (default: 1mhz) clk_1m_o 18 o feedback of free running clock reset_b 19 i system reset ( active low) hsync_x 41 o default hsync generated by asic (active low) vsync_x 42 o default vsync generated by asic (active low) r_osd 20 i osd color red g_osd 21 i osd color green b_osd 22 i osd color blue en_osd 23 i osd mixer enable =0, no osd output =1,r_out[7:0]= {r_osd repeat 8 times} g_out[7:0]= {g_osd repeat 8 times } b_out[7:0]= {b_osd repeat 8 times }
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 13 revision b scan_en 24 i manufacturing test pin (nc) test_en 25 i manufacturing test pin (nc) vdd 17 power supply vdd 36 power supply vdd 45 power supply vdd 46 power supply vdd 56 power supply vdd 67 power supply vdd 77 power supply vdd 91 power supply vdd 92 power supply vdd 99 power supply vdd 109 power supply vdd 119 power supply vdd 129 power supply vdd 141 power supply vdd 150 power supply vdd 160 power supply gnd 12 ground gnd 35 ground gnd 43 ground gnd 48 ground gnd 51 ground gnd 61 ground gnd 71 ground gnd 72 ground gnd 82 ground gnd 83 ground gnd 94 ground gnd 104 ground gnd 116 ground gnd 124 ground gnd 135 ground gnd 146 ground gnd 156 ground
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 14 revision b 3. functional description the sd1 2 10 has the following major function blocks: 1. input mode detection and auto calibration block 2. buffer memory and read/write control block 3. image scaling, interpolation and dithering block 4. osd mixer and lcd interface block 5. eeprom interface block 6. cpu interface block the following sections will describe the functionality of these blocks. 3.1. input mode detection & auto calibration block 3.1.1. supported input modes sd1 2 10 can handle up to 14 different input modes. for sd1 2 10 , an input mode is defined by its horizontal resolution with its vertical resolution. the input modes with the same horizontal and vertical resolution but with different frame rates are still considered as one single input mode. in the default eeprom setup, sd1 2 10 accepts the following eleven input video modes: 1. 640 x 350 2. 640 x 400 3. 720 x 400 4. 640 x 480 (vga) 5. 800 x 600 (svga) 6. 832 x 624 (mac) 7. 1024 x 768 (xga) 8. 1152 x 864 9. 1152 x 870 10. 1280 x 960 11. 1280 x 1024 (sxga) users can easily change the definitions of the acceptable input modes by adjusting the values in the appropriate eeprom entries. there is no frame rate restriction on the input modes. however, since the output signal is synchronized with the input signal at the same refresh rate, the input refresh rate has to be within the acceptable range of the lcd panel. the user-defined video modes can be defined by storing appropriate timing information in the eeprom. detail definitions of the eeprom entries are described
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 15 revision b in section 3.5.2. 3.1.2. input mode detection and frequency detection the sd1 2 10 can automatically detect the mode of the input signal without any user adjustment or driver running on the pc host or external cpu. this block automatically detects polarity of input synchronization and the sizes of back porch, valid data window and the synchronization pulse width in both vertical and horizontal directions. the size information is then used not only to decide the input resolution, to generate the frequency divider for the input pll, to lock the pll output clock with hsync, but also to automatically scale the image to full screen and to synchronize the output signal with the input signal. the detection logic is always active to automatically detect any changes to the input mode. users can manually change the input mode information at run time through the cpu interface. detailed operation of the cpu interface is described in section 3.6. ?cpu interface?. mode detection and frequency detection can be independently turned on or off by the external cpu. this feature allows system customers to have better control of the mode-detection and frequency detection process. when the detection is turned off, the external cpu can change the input mode and frequency definitions. 3.1.3. phase calibration the sd1 2 10 can automatically calibrate the phase of the sample clock in order to preserve the bandwidth of the input signal and to get the best quality. the sd1 2 10 implements a proprietary image quality function. during the auto-calibration process, the sd1 2 10 continues to search for the best phase to optimize the image quality. the output image may display some jitter and blurring during the auto-calibration process, and the image will become crisp and sharp once the optimum phase is found. user can change the sampling clock phase value through the external cpu. detailed operation of the cpu interface is described in section 3.6. ?cpu interface?. the phase calibration process can be delayed and even disabled by the external cpu if the system designer wants to have his/her own implementation. the phase calibration can be independently turned on or off by the external cpu. when the calibration is turned off, the external cpu can change the input mode and frequency definitions. 3.1.4. pwm operation the sd1 2 10 implements a unique algorithm to adjust the phase of the a/d converter?s sampling clock. an external delay circuit is required to compliment the sd1 2 10 for the phase-calibration process. the sd1 2 10 generates a pulse-width modulated (pwm) signal to the external delay circuit. the delay circuit should insert
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 16 revision b a certain amount of time delay synchronization pulse based upon the width of the pwm signal. a brief circuit diagram for the pwm is shown in figure 3. the pwm signal from the sd1 2 10 is a periodical signal with a period that is 1023 times the period of the free-running clock connected to the pin ?clk_1m?. system manufacturers may select any frequency for the free running clock. the default clock frequency is 1mhz. system manufacturers also decide the unit delay for the external delay circuit. the delay information is stored in the eeprom. when the sd1 2 10 wants to delay the synchronization pulse for n units of delay, it will output the pwm with the high time equal to (n * the period of the free-running clock), and with low time equal to (1023-n)* the period of the free-running clock. when n=1023, the pwm signal stays high all the time, and when n=0, the pwm signal is always low. figure 3: sd1 2 10 pwm circuitry block diagram 3.1.5. free running clock as described in previous section, a free-running clock is needed for the sd1 2 10 . this clock is used for many of the sd1 2 10 ?s internal operations. pwm operation is one of them. system manufacturers can select the frequency of the free-running clock, and the default clock frequency is 1mhz. system manufacturers can use an oscillator to generate the free-running clock, and feed that clock directly to the pin ?clk_1m?, or use a crystal connecting to ?clk_1m? and ?clk_1m_o?. 3.2. buffer memory and read/write control block the sd1 2 10 uses internal buffer memory to store a portion of the input image for image scaling and output synchronization. no external memory buffer is needed for the sd1 2 10 . the write control logic ensures the input data are stored into the right area of the buffer memory, and the read control logic is responsible to fetch the data from the buffer memory from the correct area and at the correct timing sequence. with the precise timing control of the write and read logic, the output image is sd1 2 10 pwm delay circuitry synchronization pulse pll ref_clk
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 17 revision b appropriately scaled to the full screen, and the output signal is perfectly synchronized with the input signals. 3.3. image scaling, interpolation and dithering block the sd1 2 10 supports both automatic image scaling and interpolation. 3.3.1. image scaling the sd1 2 10 supports several different input modes, and the input image may have different sizes. it is essential to support automatic image scaling so that the input image is always displayed to the full screen regardless the input mode. the sd1 2 10 scales the images in both horizontal and vertical directions. it calculates the correct scaling ratio for both directions based upon the lcd panel resolution and the input mode and timing information produced by the ?input mode detection & auto calibration? block. the scaling ratio is re-adjusted whenever a different input mode is detected. the ratio is then fed to the buffer memory read control logic to fetch the image data with the right sequence and timing. some of the image data may be read more than once to achieve the scaling effect. 3.3.2. image interpolation the sd1 2 10 supports image interpolation to achieve better image quality. a basic image scaling algorithm replicates the input images to achieve the scaling effect. the replication scheme usually results in a poor image quality. the sd1 2 10 implements a proprietary interpolation algorithm to improve the image quality . the programmable interpolation is implemented with a 256-entry mapping table in the eeprom to allow system users to adjust the bi-linear interpolation parameters to control the sharpness and smoothness quality of the image. in the default setting, the mapping table contains a straight line of slope equal to 1, i.e. the data in entry n equal to the value n. if the mapping table contains a line of slope equal to 2, then the output image will be a bit sharper than the image generated by a table with the default setting. through an external microcontroller, users can chose among different interpolation algorithm. 3.3.3. dithering the sd1 2 10 supports 16.7 million true colors for a 6-bit panel. two dithering algorithms are implemented and users can chose between them through the external microcontroller. the first one is area-based dithering, and the second one is a frame- based frame modulation, which also is called frame rate control. through the external microcontroller, users can choose among different dithering algorithms.
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 18 revision b 3.3.4. text enhancement in order to generate a good picture, the sd1 2 10 incorporate a proprietary scheme to detect text and non-text picture. then applying the appropriate process to improve the text image base d on the detection of incomin g source . by using the text enhancement function correctly , the text image will be l ooked more pleasant and near perfect after scaled up or down. users can achieve a preferred image by changing the setting s in ?text control? register. 3.3.5. sharpness enhancement no matter how many times the original image got enlarged or shrunk by the internal interpolator. with the embedded powerful dsp array s , sd1 2 10 always can enhance the overall image sharpness (edge) to different degree for the various requirements. the sharpness can be adjusted bi-directionally which means either going sharper or softer to certain point set by the user. it ?s easy to activate the sharpness enhancement by program ?sharpness control? register. 3.4. osd mixer and lcd interface at the output stage, the sd1 2 10 performs the osd mixer function, and then generates the 24-bit / 48-bit rgb signal to the lcd panel with the correct timing. 3.4.1. osd mixer in the osd mixer block, the sd1 2 10 mixes the normal output rgb signal with the osd signal. the osd output data is generated based on the ?r_osd?, ?g_osd? and ?b_osd? pins as well as the ?osd intensity? data in eeprom entry. when the ?en_osd? is active high, the osd is active, and the sd1 2 10 will send the osd data to the lcd panel. the osd has 16 different color schemes based on the combinations of the three osd color pins and the ?osd intensity? data. when r_osd=1, and osd_intensity=0, the sd10 10 will output 128 to the output red channel, r_out. when r_osd=1 and osd_intensity=1, the sd1 2 10 will output 255. the same scheme is used for g_osd to g_out and for b_osd to b_out. as part of the mixer control function, the sd1 2 10 implements three mixing control registers, ?osd r weight? (38h), ?osd g weight?(39h), and ?osd b weight? (3ah). the mixing equation is shown below: r_out = (r_osd) * (osd r weight/255) + r * (1 - osd r weight/255) g_out = (g_osd) * (osd g weight/255) + g * (1 - osd g weight/255) b_out = (b_osd) * (osd b weight/255) + b * (1 - osd b weight/255)
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 19 revision b when the weight is 255, the osd output will overlay on top of the normal output. when the weight is 0, the osd output is disabled. 3.4.2. lcd interface the sd1 2 10 support both 24- and 48-bit rgb interfaces with s xga lcd panels from various panel manufacturers. the lcd panel resolution and timing information is stored in the external eeprom. the information in the eeprom includes timing related to the output back porch, synchronization pulse width and valid data window. the timing information is used to generate the frequency divider for the output pll, to lock the pll output clock with hsync for the lcd data clock, and to synchronize the output vsync and input vsync. 3.5. eeprom interface as mentioned in previous sections, the external eeprom stores crucial information for the sd1 2 10 internal operations. the sd1 2 10 interfaces with the eeprom through a 2-wire serial interface. the suggested eeprom device is an industry standard serial-interface eeprom (24x08). the 2-wire serial interface scheme is briefly described here and a detailed description can be found in public literature. 3.5.1. 2-wire serial interface the 2-wire serial interface uses 2 wires, scl and sda. the scl is driven by the sd1 2 10 and used mainly as the sampling clock. the sda is a bi-directional signal and used mainly as a data signal. figure 4 shows the basic bit definitions of the 2-wire serial interface. the 2-wire serial interface supports random and sequential read operations. figures 5 and 6 show the data sequences for random read and sequential read operations.
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 20 revision b figure 4: start, stop and data definitions in 2-wire serial interface sda scl start stop data change data stable data change
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 21 revision b figure 5: data sequence for read access (both single and multiple bytes) l s b b i t 0 l s b b i t 0 l s b b i t 0 s t o p device address [6:0] a c k m s b b i t 6 a c k data read m s b b i t 7 a c k s t a r t w r i t e word address [5:0] device address [6:0] m s b b i t 6 r /_ w a c k m s b b i t 7 s t a r t s t o p r e a d
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 22 revision b figure 6: data sequence for write access (both single and multiple bytes) 3.5.2. eeprom contents the contents of eeprom are primarily dependent on the specifications of the lcd panel. smartasic provides suggested eeprom contents for lcd panels from various panel manufacturers. the section presents all the entries in the eeprom, and briefly describes their definitions. this allows the system manufacturers to have their own eeprom contents to distinguish their monitors. the eeprom contents can be partitioned into 15 parts. the first 14 parts are input mode dependent. when the sd1 2 10 detects the input mode, it will then load the information related to the detected mode from the eeprom. the information in the 15 th part is mainly for input mode detection as well as some threshold values for error status indicators. in the default setting, the sd1 2 10 is set to recognize the following eleven modes: 640x350, 640x400, 720x400, 640x480, 800x600, 832x624, 1024x768 , 1152x864, 1152x870, 1280x960, and 1280x1024 modes. then the eeprom will be partitioned as follows: s t o p data n a c k l s b b i t 0 m s b b i t 7 a c k data n+x l s b b i t 0 m s b b i t 7 a c k s t a r t w r i t e word address [5:0] device address [6:0] l s b b i t 0 m s b b i t 6 r /_ w a c k m s b b i t 7
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 23 revision b part 1: mode 1: 640x350 mode (in default setting) part 2: mode 2: 640x400 mode (in default setting) part 3: mode 3: 720x400 mode (in default setting) part 4: mode 4: 640x480 mode (in default setting) part 5: mode 5: 800x600 mode (in default setting) part 6: mode 6: 832x624 mode (in default setting) part 7: mode 7: 1024x768 mode (in default setting) part 8: mode 8 : 1152x864 mode (in default setting) part 9: mode 9 : 1152x970 mode (in default setting) part 10: mode 10 : 1280x960 mode (in default setting) part 11: mode 11 : 1280x1024 mode (in default setting) part 12: mode 12 part 13: mode 13 part 14: mode 14 part 15: input mode detection and scaling related parameters
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 24 revision b part 1-14: input mode dependent data symbol width (bits) address for 640x350 description vpw 11 00h 01h lcd vsync pulse width vbp 11 02h 03h lcd vsync back porch (including vpw) vbp source 11 04h 05h lcd vsync back porch (source equivalent) = vbp * line expansion and round up target skip pixel 11 06h 07h if vbp can not be converted into source evenly, the leftover is converted into number of pixels vsize 11 08h 09h lcd number of lines hpw 11 0ah 0bh lcd hsync pulse width hbp 11 0ch 0dh lcd hsync back porch (including hpw) hsize 11 0eh 0fh lcd number of columns htotal 11 10h 11h lcd total number of pixels per line including all porches htotal source 12 12h 13h lcd total number of clocks per line (source equivalent) = htotal/line expansion line expansion 4 14h [6:3] vertical source-to-destination scaling factor 0: one-to-one expansion (no expansion) 1-15: expansion ratio other than one-to-one (expansion) pixel expansion 3 14h [2:0] horizontal source-to-destination scaling factor 0: one-to-one expansion (no expansion) 1-7: expansion ratio other than one-to-one (expansion) h. fog factor 8 15h[7:0] horizontal fogging factor high byte h. fog factor 8 16h[7:0] horizontal fogging factor low byte v. fog factor 8 17h[7:0] vertical fogging factor high byte v. fog factor 8 18h[7:0] vertical fogging factor low byte minimum input lines [10:8] 3 19h[6:4] upper 3 bits of minimum input lines maximum input pixels [10:8] 3 19h[2:0] upper 3 bits of maximum input pixels minimum input lines [7:0] 8 1ah minimum input lines = (vsize + vbp)* line expansion when the input has fewer lines than this value, it is considered as an error, and input_x status bit will be high. maximum input pixels [7:0] 8 1bh maximum input pixels per line. auto clock recovery will not set input pll divisor larger than this value. source hsize[10:8] 3 1ch [6:4] source horizontal size upper 3 bits source 3 1ch [2:0] source vertical size upper 3 bits
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 25 revision b vsize[10:8] source hsize[7:0] 8 1dh source horizontal size lower 8 bits source vsize[7:0] 8 1eh source vertical size lower 8 bits check sum 8 1fh sum of above 31 bytes (keep lower 8 bits only) mode address range 640x400 20h 3fh 720x400 40h 5fh 640x480 60h 7fh 800x600 80h 9fh 832x624 a0h bfh 1024x768 c0h dfh 1152x864 e0h ffh 1152x870 100h 11fh 1280x960 120h 13fh 1280x1024 140h 15fh user define mode 1 160h 17fh user define mode 2 180h 19fh user define mode 3 1a0h 1bfh part 15: input mode detection data symbol width (bits) address description control byte 0 8 200h bit 6 ? bit 0 : device id for external cpu access bit 7: 0: select internal generated h/v sync 1: select external input h/v sync control byte 1 8 201 h bit0: 0: disable automatic input gain control 1: enable automatic input gain control bit1: 0: enable input h/v sync polarity control (make input sync positive polarity) 1: bypass input h/v sync polarity control
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 26 revision b bit2: 0: single pixel input 1: dual pixel input bit3: 0: disable digital input 1: enable digital input bit4: 0: yuv input format is unsigned (128 offset) 1: yuv input format is signed bit5: 0: rgb input for video mode 1: yuv input for video mode bit6: 0: disable video input 1: enable video input bit7: 0: disable decimation support 1: enable decimation control byte 2 8 202h bit 0: 0: don?t invert input odd/even field indicator 1: invert input odd/even field indicator bit 1: 0: disable half clock mode for dual pixel input 1: enable half clock mode for dual pixel input bit 2: 0: disable by2 for auto calibration 1: enable by 2 for auto calibration bit 3 : 0: disable by 4 for auto calibration 1: enable by 4 for auto calibration bit 4 : 0: disable by 8 for auto calibration 1: enable by 8 for auto calibration bit7-5: output clock phase adjustment, larger number gives larger phase delay. mode 640x350 sync polarity 2 203 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res0 threshold [10:8] 3 203 h[2:0] upper bound of the line number for 640x350 mode res0 threshold [7:0] 8 204 h upper bound of the line number for 640x350 mode, and lower bound for 640x400 mode 640x400 sync polarity 2 205 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res1 threshold [10:8] 3 205 h[2:0] upper bound of the line number for 640x400 mode res1 threshold [7:0] 8 206 h upper bound of the line number for 640x400 mode, and lower bound for 720x400 mode 720x400 sync polarity 2 207 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res2 threshold [10:8] 3 207 h[2:0] upper bound of the line number for 720x400 mode res2 threshold [7:0] 8 208 h upper bound of the line number for 720x400 mode, and lower bound for 640x480 mode 640x480 sync polarity 2 209 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res3 threshold [10:8] 3 209 h[2:0] upper bound of the line number for 640x480 mode res3 threshold [7:0] 8 20a h upper bound of the line number for 640x480 mode, and lower bound for 800x600 mode 800x600 sync polarity 2 20b h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res4 threshold [10:8] 3 20b h[2:0] upper bound of the line number for 800x600 mode res4 threshold 8 20c h upper bound of the line number for 800x600 mode, and
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 27 revision b [7:0] lower bound for 832x624 mode 832x624 sync polarity 2 20d h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res5 threshold [10:8] 3 20d h[2:0] upper bound of the line number for 832x624 mode res5 threshold [7:0] 8 20e h upper bound of the line number for 832x624 mode, and lower bound for 1024x768 mode 1024x768 sync polarity 2 20f h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res6 threshold [10:8] 3 20f h[2:0] upper bound of the line number for 1024x768 mode res6 threshold [7:0] 8 210 h upper bound of the line number for 1024x768 mode , and lower bound for 1152x864 mode 1152x864 sync polarity 2 211 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync r es7 threshold [10:8] 3 211 h[2:0] upper bound of the line number for 1152x864 mode. res 7 threshold [7:0] 8 212 h upper bound of the line number for 1152x864 mode, and lower bound for 1152x870 mode 1152x870 sync polarity 2 213 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res 8 threshold [10:8] 3 213 h[2:0] upper bound of the line number for 1152x870 mode. res 8 threshold [7:0] 8 214 h upper bound of the line number for 1152x870 mode, and lower bound for 1280x960. mode 1280x960 sync polarity 2 215 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res 9 threshold [10:8] 3 215 h[2:0] upper bound of the line number for 1280x960 mode. res 9 threshold [7:0] 8 216 h upper bound of the line number for 1280x960 mode, and lower bound for 1280x1024. mode 1280x1024 sync polarity 2 217 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync res 10 threshold [10:8] 3 217 h[2:0] upper bound of the line number for 1280x1024 mode. re s10 threshold [7:0] 8 218 h upper bound of the line number for 1280x1024 mode. reserve mode 1 sync polarity 2 219 h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync reserve mode 1 res threshold [10:8] 3 219 h[2:0] resolution threshold for reserve mode 1 reserve mode 1 res threshold [7:0] 8 21a h resolution threshold for reserve mode 1 reserve mode 2 sync polarity 2 21b h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync reserve mode 2 res threshold [10:8] 3 21b h[2:0] resolution threshold for reserve mode 2 reserve mode 2 res threshold [7:0] 8 21c h resolution threshold for reserve mode 2 reserve mode 3 sync polarity 2 21d h[5:4] the polarity of input synchronization signals. bit 0 is for vsync and bit 1 is for hsync reserve mode 3 res threshold [10:8] 3 21d h[2:0] resolution threshold for reserve mode 3
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 28 revision b reserve mode 3 res threshold [7:0] 8 21e h resolution threshold for reserve mode 3 enable sync check 14 21f h- 220 h enable sync polarity check during input mode detection. 1: enable sync polarity based mode detection 0: disable sync polarity based mode detection bit 0: 640x350 bit 1: 640x400 bit 2: 720x400 bit 3: 640x480 bit 4: 800x600 bit 5: 832x624 bit 6: 1024x768 bit 7: 1152x864 bit 8: 1152x870 bit 9: 1280x960 bit 10: 1280x1024 bit 11: res mode 1 bit 12: res mode 2 bit 13: res mode 3 maximum vbp 8 221 h the maximum vertical back porch for input video mode0 vertical size 11 222h-223h mode0 vertical size for digital input mode1 vertical size 11 224h-225h mode1 vertical size for digital input mode2 vertical size 11 226h-227h mode2 vertical size for digital input mode3 vertical size 11 228h-229h mode3 vertical size for digital input mode4 vertical size 11 22ah-22bh mode4 vertical size for digital input mode5 vertical size 11 22ch-22dh mode5 vertical size for digital input mode6 vertical size 11 22eh-22fh mode6 vertical size for digital input mode7 vertical size 11 230h-231h mode7 vertical size for digital input mode8 vertical size 11 232h-233h mode8 vertical size for digital input mode9 vertical size 11 234h-235h mode9 vertical size for digital input mode10 vertical size 11 236h-237h mode10 vertical size for digital input mode11 vertical size 11 238h-239h mode11 vertical size for digital input mode12 vertical size 11 2 3a h-23bh mode12 vertical size for digital input mode0 horizontal size 11 23ch-23dh mode0 horizontal size for digital input mode1 horizontal size 11 23eh-23fh mode1 horizontal size for digital input mode2 horizontal size 11 240h-241h mode2 horizontal size for digital input mode3 horizontal size 11 242h-243h mode3 horizontal size for digital input mode4 horizontal size 11 244h-245h mode4 horizontal size for digital input mode5 horizontal size 11 246h-247h mode5 horizontal size for digital input mode6 horizontal size 11 248h-249h mode6 horizontal size for digital input mode7 horizontal size 11 24 a h-24bh mode7 horizontal size for digital input mode8 horizontal size 11 24ch-24dh mode8 horizontal size for digital input mode9 horizontal size 11 24eh-24fh mode9 horizontal size for digital input mode10 horizontal size 11 250h-251h mode10 horizontal size for digital input mode11 horizontal size 11 252h-253h mode11 horizontal size for digital input mode 12 horizontal size 11 254h-255h mode12 horizontal size for digital input data low threshold 8 256h low water mark for valid data. if the data is smaller than this threshold, it is considered low internally data high threshold 8 257h high water mark for valid data. if the data is larger than this threshold, it is considered high internally edge threshold 8 258h minimum difference between the data value of two adjacent pixels to be considered as an edge calibration mode 2 259h [1:0] selects different operation modes of internal phase calibration. the selection criterion is as follows: 0: when input video signal has large overshot, it results in longest calibration time 1: when input video signal has median overshot, it results in long calibration time 2: when input video signal has normal overshot,
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 29 revision b it results in normal calibration time (recommended) 3: when input video signal has no overshot, it results in shortest calibration time pwm unit delay 1 6 25a h- 25b h the unit delay used in the external pwm delay circuitry. if the free-running clock is 1mhz, and the intended unit delay is 0.2 ns (= 5,000mhz), then a value of 5,000mhz/1mhz = 5,000 is used here. maximum link off time 22 25c h- 25e h maximum time when input vsync is off before the link_dwn pin turns on (unit: clock period of the free running clock). if the free-running clock is 1mhz, and the intended maximum time is 1 second, then a value of 1,000,000 m s/ 1 m s = 1,000,000 is used here. maximum refresh rate 16 25f h- 260 h maximum refresh rate supported by the lcd panel. if the intended maximum refresh rate is 75hz, and the free-running clock is 1mhz, then a value of 1000000/75=133,333 is used here maximum input frequency 8 261 h maximum source clock rate supported by the sd1010 (unit: frequency of free-running clock). if the intended maximum clock rate is 60mhz, and the free-running clock is 1mhz, then a value of 60 is used here. if the input signal has a higher frequency than this value, the vclk0_x status bit will turn on. minimum pixels per line for lcd 11 262h - 263 h minimum number of pixels per line for lcd panel lcd polarity 4 264 h[3:0] controls the polarity of output vsync, hsync, clock and display enable: bit0: 0: clock active high, 1: clock active low bit1: 0: hsync active low, 1: hsync active high bit2: 0: vsync active low, 1: vsync active high bit4: 0: de active high, 1: de active low output enable for output pin 51-54, 56-59, 61-64, 66-69, 71-74, 76-79, 81- 84, 86-89, 91-97, 99, 101-104, 106-109 1 265 h[3] enable for programmable output pad: 1: output is enabled 0: output is tri-state driving capability control for output pin 51-54, 56-59, 61-64, 66- 69, 71-74, 76-79, 81-84, 86-89, 91-97, 99, 101- 104, 106-109 3 265 h[2:0] 0: 2ma 1: 6ma 2: 6ma 3: 10ma 4: 4ma 5: 8ma 6: 8ma 7: 12ma output enable for output pin 49 (de) 1 266 h[7] enable for programmable output pad: 1: output is enabled 0: output is tri-state driving capability control for output pin 49 (de) 3 266 h[6:4] 0: 2ma 1: 6ma 2: 6ma 3: 10ma 4: 4ma 5: 8ma
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 30 revision b 6: 8ma 7: 12ma output enable for output pin 46 (hsync_o) 1 266 h[3] enable for programmable output pad: 1: output is enabled 0: output is tri-state driving capability control for output pin 46 (hsync_o) 3 266 h[2:0] 0: 2ma 1: 6ma 2: 6ma 3: 10ma 4: 4ma 5: 8ma 6: 8ma 7: 12ma output enable for output pin 49 (vsync_o) 1 267 h[7] enable for programmable output pad: 1: output is enabled 0: output is tri-state driving capability control for output pin 49 (vsync_o) 3 267 h[6:4] 0: 2ma 1: 6ma 2: 6ma 3: 10ma 4: 4ma 5: 8ma 6: 8ma 7: 12ma output enable for output pin 46 (dclk_out) 1 267 h[3] enable for programmable output pad: 1: output is enabled 0: output is tri-state driving capability control for output pin 46 (dclk_out) 3 267 h[2:0] 0: 2ma 1: 6ma 2: 6ma 3: 10ma 4: 4ma 5: 8ma 6: 8ma 7: 12ma extension right 4 268h[7:4] numbers of pixels extended right for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification extension left 4 268h[3:0] numbers of pixels extended left for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification extension down 2 269h[1:0] numbers of lines extended down for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification gamma_format0 24 26ah-26ch 26ah: gamma_format0_red 26bh: gamma_format0_ green 26ch: gamma_format0_blue gamma_format1 24 26dh-26fh 26dh: gamma_format1_red 26eh: gamma_format1_green 26fh: gamma_format1_blue gamma_th0_r 8 270h gamma_threshold0 for red gamma_th1_r 8 271h gamma_threshold1 for red gamma_th2_r 8 272h gamma_threshold2 for red gamma_th3_r 8 273h gamma_threshold3 for red
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 31 revision b gamma_th4_r 8 274h gamma_threshold4 for red gamma_th5_r 8 275h gamma_threshold5 for red gamma_th6_r 8 276h gamma_threshold6 for red gamma_th0_g 8 277h gamma_threshold0 for green gamma_th1_g 8 278h gamma_threshold1 for green gamma_th2_g 8 279h gamma_threshold2 for green gamma_th3_g 8 27ah gamma_threshold3 for green gamma_th4_g 8 27bh gamma_threshold4 for green gamma_th5_g 8 27ch gamma_threshold5 for green gamma_th6_g 8 27dh gamma_threshold6 for green gamma_th0_b 8 27eh gamma_threshold0 for blue gamma_th1_b 8 27fh gamma_threshold1 for blue gamma_th2_b 8 280h gamma_threshold2 for blue gamma_th3_b 8 281h gamma_threshold3 for blue gamma_th4_b 8 282h gamma_threshold4 for blue gamma_th5_b 8 283h gamma_threshold5 for blue gamma_th6_b 8 284h gamma_threshold6 for blue gamma_scale0_r 8 285h gamma_ scalefactor0 for red gamma_scale1_r 8 286h gamma_scalefactor1 for red gamma_scale2_r 8 287h gamma_scalefactor2 for red gamma_scale3_r 8 288h gamma_scalefactor3 for red gamma_scale4_r 8 289h gamma_scalefactor4 for red gamma_scale5_r 8 28ah gamma_scalefactor5 for red gamma_scale6_r 8 28bh gamma_scalefactor6 for red gamma_scale7_r 8 28ch gamma_scalefactor7 for red gamma_scale0_g 8 28dh gamma_scalefactor0 for green gamma_scale1_g 8 28eh gamma_scalefactor1 for green gamma_scale2_g 8 28fh gamma_scalefactor2 for green gamma_scale3_g 8 290h gamma_scalefactor3 for green gamma_scale4_g 8 291h gamma_scalefactor4 for green gamma_scale5_g 8 292h gamma_scalefactor5 for green gamma_scale6_g 8 293h gamma_scalefactor6 for green gamma_scale7_g 8 294h gamma_scalefactor7 for green gamma_scale0_b 8 295h gamma_scalefactor0 for blue gamma_scale1_b 8 296h gamma_scalefactor1 for blue gamma_scale2_b 8 297h gamma_scalefactor2 for blue gamma_scale3_b 8 298h gamma_scalefactor3 for blue gamma_scale4_b 8 299h gamma_scalefactor4 for blue gamma_scale5_b 8 29ah gamma_scalefactor5 for blue gamma_scale6_b 8 29bh gamma_scalefactor6 for blue gamma_scale7_b 8 29ch gamma_scalefactor7 for blue gamma_offset0_r 8 29dh gamma_offset0 for red gamma_offset1_r 8 29eh gamma_offset1 for red gamma_offset2_r 8 29fh gamma_offset2 for red gamma_offset3_r 8 2a0h gamma_offset3 for red gamma_offset4_r 8 2a1h gamma_offset4 for red gamma_offset5_r 8 2a2h gamma_offset5 for red gamma_offset6_r 8 2a3h gamma_offset6 for red gamma_offset7_r 8 2a4h gamma_offset7 for red gamma_offset0_g 8 2a5h gamma_offset0 for green gamma_offset1_g 8 2a6h gamma_offset1 for green gamma_offset2_g 8 2a7h gamma_offset2 for green
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 32 revision b gamma_offset3_g 8 2a8h gamma_offset3 for green gamma_offset4_g 8 2a9h gamma_offset4 for green gamma_offset5_g 8 2aah gamma_offset5 for green gamma_offset6_g 8 2abh gamma_offset6 for green gamma_offset7_g 8 2ach gamma_offset7 for green gamma_offset0_b 8 2adh gamma_offset0 for blue gamma_offset1_b 8 2aeh gamma_offset1 for blue gamma_offset2_b 8 2afh gamma_offset2 for blue gamma_offset3_b 8 2b0h gamma_offset3 for blue gamma_offset4_b 8 2b1h gamma_offset4 for blue gamma_offset5_b 8 2b2h gamma_offset5 for blue gamma_offset6_b 8 2b3h gamma_offset6 for blue gamma_offset7_b 8 2b4h gamma_offset7 for blue check sum 8 2b5 h sum of all part 9 bytes (keep only lower 8 bit) 3.6. cpu interface the sd1 2 10 supports a 2-wire serial interface to an external cpu. the interface allows the external cpu to access and modify control registers inside the sd1 2 10 . the 2-wire serial interface is similar to the eeprom interface, and the cpu is the host that drives the scl all the time as the clock and for ?start? and ?stop? bits. the scl frequency can be as high as 5mhz. the sda is a bi-directional data wire. this interface supports random and sequential write operations for the cpu to modify one or multiple control registers, and random and sequential read operations for the cpu to read all or part of the control registers. the default device id for the sd1 2 10 is fixed ?1111111 ?. the device id can be programmed through eeprom entry 200h bit 0 through bit 6. this avoids any conflict with other 2-wire serial devices on the same bus. the following table briefly describes the sd1 2 10 control registers. the external cpu can read these registers to know the state of the sd1 2 10 as well as the result of input mode detection and phase calibration. the external cpu can modify these control registers to disable several sd1 2 10 features and force the sd1 2 10 into a particular state. when the cpu modifies the control registers, the new data will be first stored in a set of shadow registers, and then copied into the actual control registers when the ?cpu control enable? bit is set. when the ?cpu control enable? bit is set, the external cpu will retain control and the sd1 2 10 will not perform the auto mode detection and auto calibration. the external cpu is able to adjust the size of the output image and move the output image up and down by simply changing the porch size and pixel and line numbers of the input signal. these adjustments can be tied to the external user control button on the monitor.
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 33 revision b a set of four control registers are used to generate output signal when there is no input signal available to the sd1 2 10 or the input signal is beyond the acceptable ranges. this operation mode is called standalone mode, which is very important for the end users when they accidentally select an input mode beyond the acceptable range of the sd1 2 10 or when the input cable connection becomes loose for any reason. system manufacturers can display appropriate osd warning messages on the lcd panel to notify the users about the problem. table 3: sd1 2 10 control registers symbol width mode address description vbp source 11 rw 0h-1h input vsync back porch (not include pulse width) vsize source 11 rw 2h-3h input image lines per frame vtotal source 11 rw 4h-5h input total number of lines including porches hbp source 11 rw 6h-7h input hsync back porch (not include pulse width) hsize source 11 rw 8h-9h input image pixels per line htotal source 11 rw ah-bh input total number of pixels per line including porches mode source 4 rw ch[3:0] input video format 0: 640x350 1: 640x400 2: 720x400 3: 640x480 4: 800x600 5: 832x624 6: 1024x768 7: user defined mode 1 8: user defined mode 2 9: user defined mode 3 10: user defined mode 4 11: user defined mode 5 12: user defined mode 6 13: user defined mode 7 14-15: error clock phase source 10 rw dh-eh input sampling clock phase vpw standalone 11 rw fh-10h for standalone mode, the pulse width of vsync vtotal standalone 11 rw 11h-12h for standalone mode, total number of line per frame hpw standalone 11 rw 13h-14h for standalone mode, hsync active time in m s htotal standalone 11 rw 15h-16h for standalone mode, hsync cycle time in m s disable auto calibration for mode 640x350 1 rw 17h[7] disable auto calibration for this mode: 1: disable 0: enable delay auto calibration for mode 640x350 15 rw 17h[6:0]- 18h the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 640x400 1 rw 19h[7] disable auto calibration for this mode: 1: disable 0: enable delay auto calibration for mode 640x400 15 rw 19h[6:0]- 1ah the number of frames need to be skipped before starting auto calibration for this mode disable auto 1 rw 1bh[7] disable auto calibration for this mode:
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 34 revision b calibration for mode 720x400 1: disable 0: enable delay auto calibration for mode 720x400 15 rw 1bh[6:0]- 1ch the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 640x480 1 rw 1dh[7] disable auto calibration for this mode: 1: disable 0: enable delay auto calibration for mode 640x480 15 rw 1dh[6:0]- 1eh the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 800x600 1 rw 1fh[7] disable auto calibration for this mode: 1: disable 0: enable delay auto calibration for mode 800x600 15 rw 1fh[6:0]- 20h the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 832x624 1 rw 21h[7] disable auto calibration for this mode: 1: disable 0: enable delay auto calibration for mode 832x624 15 rw 21h[6:0]- 22h the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 1024x768 1 rw 23h[7] disable auto calibration for this mode: 1: disable 0: enable delay auto calibration for mode 1024x768 15 rw 23h[6:0]- 24h the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode invalid 1 rw 25h[7] disable auto calibration for this mode: 1: disable 0: enable delay auto calibration for mode invalid 15 rw 25[6:0]- 26h the number of frames need to be skipped before starting auto calibration for this mode bypass sync polarity 1 rw 27h[7] bypass input sync polarity detection (default 0): 1: bypass input sync polarity detection 0: detect input sync polarity and make them negative polarity dithering enable 1 rw 28h[7] enable dithering for 6-bit panel (default 0): 1: enable dithering 0: disable dithering *also check register control_c[6] frame modulation enable 1 rw 28h[6] enable frame modulation for 6-bit panel (default 0): 1: enable frame modulation 0: disable frame modulation *also check register control_b[5] and control_b[7] horizontal interpolation enable 1 rw 28h[5] enable horizontal interpolation (default 0): 1: enable horizontal interpolation 0: disable horizontal interpolation vertical interpolation enable 1 rw 28h[4] enable vertical interpolation (default 0): 1: enable vertical interpolation 0: disable vertical interpolation horizontal rounding 1 rw 28h[3] enable horizontal rounding (default 0):
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 35 revision b enable 1: enable horizontal rounding 0: disable horizontal rounding vertical rounding enable 1 rw 28h[2] enable vertical rounding (default 0): 1: enable vertical rounding 0: disable vertical rounding horizontal table lookup enable 1 rw 28h[1] enable horizontal table lookup (default 0): 1: enable horizontal table lookup 0: disable horizontal table lookup vertical table lookup enable 1 rw 28h[0] enable vertical table lookup (default 0): 1: enable vertical table lookup 0: disable vertical table lookup hsync threshold enable 1 rw 29h[4] enable detection of short lines (ibm panel only, default 0): 1: enable such detection 0: disable such detection osd intensity 1 rw 29h[3] osd intensity selection: 0: half intensity 1: full intensity load all eeprom 1 rw 29h[2] should be kept low most of the time. a high pulse will force sd1 2 10 to reload all eeprom entries load mode dependent eeprom 1 rw 29h[1] should be kept low most of the time. a high pulse will force sd1 2 10 to reload mode dependent eeprom entries cpu control enable 1 rw 29h[0] external cpu control enable: 0: disable external cpu control. sd1 2 10 can write control registers, but cpu only read control registers. 1: enable external cpu control. cpu can read/write control registers. sd1 2 10 cannot write control registers status 0 8 r 2ah read only internal status registers: 1: indicate error status 0: indicate normal status bit 0: eeprom vertical lookup table loading bit 1: eerpom horizontal lookup table loading bit 2: eeprom mode dependent entries loading bit 3: eeprom calibration entries loading bit 4: input has too few lines bit 5: no input video bit 6: input data clock is too fast bit 7: refresh rate exceed lcd panel specification status 1 4 r 2bh[3:0] internal auto calibration state 0: idle state 1-4: loading eeprom data 5-9: frequency calibration state (auto frequency calibration will be done after state 9) 10: phase calibration state (auto phase calibration will be done after state 10) 11: adjust horizontal back porch state 12: phase tracking state control_a 8 rw 2ch[7:0] control register a: 0 ? disable 1 ? enable default is 00h bit 0: horizontal interpolation offset enable
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 36 revision b bit 1: vertical interpolation offset enable bit 2: horizontal interpolation fraction reset enable bit 3: vertical interpolation fraction reset enable bit 4: horizontal interpolation integer increment enable bit 5: vertical interpolation integer increment enable bit 6: single pixel output mode enable bit 7: disable ?de_out?, for blanking screen purpose control_b 8 rw 2dh[7:0] control register b bit [2:0]: pixel comparison mode: 0: compare r even(default) 1: compare g even 2: compare b even 3: invalid 4: compare r odd 5: compare g odd 6: compare b odd 7: invalid *using pixel comparison should program register ?pixel comparison value? and check register ?status 2[1:0]? bit [4:3]: brightness control: 0: disable brightness control(default) 1: reduce brightness 2: increase brightness 3: invalid *using brightness control should specify register ?brightness adjustment? and check register ?status 2[2]? bit [5]: frame modulation mode: 0: 2-bit mode(default) 1: 1-bit mode bit [6]: 6-bit panel rounding enable: 0: disable(default) 1: enable bit [7]: frame modulation scheme selection: 0: scheme a(default) 1: scheme b control_c 8 rw 2eh[7:0] control register c bit [1:0]: horizontal interpolation special processing mode: 0: disable 1: linear 2: replication(default) 3: invalid bit [3:2]: vertical interpolation special processing mode: 0: disable
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 37 revision b 1: linear 2: replication(default) 3: invalid bit [4]: osd transparency enable: 0: disable(default) 1: enable *also need to program registers ?osd r weight?, ?osd g weight? and ?osd b weight? bit [5]: advanced post processing enable: 0: disable(default) 1: enable *also need to specify registers ?advanced processing r weight?, ?advanced processing g weight?, ?advanced processing b weight? , ?advanced processing r value?, ?advanced processing g value? and ?advanced processing b value? for properly functioning bit [6]: dithering scheme selection 0: scheme a(default) 1: scheme b bit [7]: reserved control_d 8 rw 2fh[7:0] control register d bit [3:0]: advanced processing shift amount. from 0 ? 8. 8 is the default value. bit [4]: advance mixing shift enable 0: disable(default) 1: enable *this is a option for advanced post processing bit [7:5]: reserved interpolation h. offset 8 rw 30h[7:0] high byte for interpolation horizontal offset default is 00h interpolation h. offset 8 rw 31h[7:0] low byte for interpolation horizontal offset default is 00h interpolation v. offset 8 rw 32h{7:0] high byte for interpolation vertical offset default is 00h interpolation v. offset 8 rw 33h[7:0] low byte for interpolation vertical offset default is 00h h. interpolation rest count 8 rw 34h[7:0] bit [2:0]: high bits for horizontal interpolation reset count. default is 0h. bit [7:3]: reserved h. interpolation reset count 8 rw 35h[7:0] low byte for horizontal interpolation reset count. default is 00h. v. interpolation reset count 8 rw 36h[7:0] bit [1:0]: high bits for vertical interpolation reset count. default is 0h. v. interpolation reset count 8 rw 37h[7:0] low byte for interpolation vertical reset count. default is 00h. osd r weight 8 rw 38h[7:0] mixing weight for osd r. default is 00h. osd g weight 8 rw 39h[7:0] mixing weight for osd g. default is 00h.
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 38 revision b osd b weight 8 rw 3ah[7:0] mixing weight for osd b. default is 00h. advanced processing r weight 8 rw 3bh[7:0] weight for advanced post processing r default is 00h advanced processing g weight 8 rw 3ch[7:0] weight for advanced post processing g default is 00h advanced processing b weight 8 rw 3dh[7:0] weight for advanced post processing b default is 00h advanced processing r value 8 rw 3eh[7:0] value for advanced post processing r default is 00h advanced processing g value 8 rw 3fh[7:0] value for advanced post processing g default is 00h advanced processing b value 8 rw 40h[7:0] value for advanced post processing b default is 00h brightness adjustment 8 rw 41h[7:0] the adjust amount for reducing/increasing brightness. default is 00h. pixel comparison value 8 rw 42h[7:0] the value to compare the incoming pixel data. default is 00h. status 2 8 r 43h[7:0] the status register 2 bit [1:0]: result for comparing the selected incoming pixel with ?pixel comparison value?: 0: invalid 1: incoming pixel > ?pixel comparison value? 2: incoming pixel = ?pixel comparison value? 3: incoming pixel < ?pixel comparison value? bit [2]: status for brightness control 0: normal, no underflow/overflow 1: brightness reduced too much causes underflow/increased too much causes overflow bit [7:3]: reserved recovery control 8 rw 44h clock recovery control register: default value is 71h bit 0: clock frequency is divisible by 2 bit 1: clock frequency is divisible by 4 bit 2: clock frequency is divisible by 8 bit 3: enable phase tracking feature bit 4: enable auto phase calibration bit 5: enable auto frequency calibration bit 6: enable auto mode detection bit 7: enable operation at half clock speed phase range 4 rw 45h offset value added to the calibrated phase when phase tracking occurs phase track waiting time 24 rw 46h 48h number of frames waited before phase tracking occurs quick phase enable 1 rw 49h[0] 0: normal phase calibration (default) 1: final phase = phase total ? phase offset pwm enable 1 rw 49h[1] 0: disable auto phase total calculation 1: enable auto phase total calculation (default) standalone enable 1 rw 49h[2] 0: uses the external incoming sync signals (default) 1: allow the use of the default sync signals instead of the incoming sync signals
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 39 revision b digital enable 1 rw 49h[3] 0: analog interface (default) 1: digital interface (no auto calibration) phase offset 10 rw 4ah 4bh offset value subtracted from phase total when doing quick phase calculation phase total 10 rw 4ch 4dh user defined value for a particular frequency image quality index 30 r 4eh[5:0],4 fh, 50h, 51h read only register for cpu to monitor image quality index. the image quality index is used by auto phase calibration. text control 8 rw 5 2 h [7:0] text-enhancement control bit[ 0]: text enhancement enable 0: disable 1: enable bit[1]: reserved bit[6:2]: text-enhanced level level 0 ? 14. level ?0? is the same as original source, and ?14? is the highest enhancement level. bit[7]: reserved default is 00h sharpness control 8 rw 5 3 h[7:0] sharpness- enhancement control bit[ 0]: sharpness enhancement enable 0: disable 1: enable bit[1]: reserved bit[6:2]: sharpness-enhanced level level 1 ? 19. level ?5? is the same as the original source. from ?4? to ?1? intend to soften the picture, and ?1? is the s oftest level. from level ?6? to ?19? will sharpen the picture gradually. level ?19? is the sharpest output. bit[7]: reserved default is 14h control_e 8 rw 5 4 h[7:0] control register e bit[3:0] : text enhancement threshold. bit[4]: reserved bit[6:5]: frame modulation mode 0: compatible with sd1 2 10 1-3: new schemes bit[7]: reserved default is 05h
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 40 revision b pixel_h 11 rw 5 5 h[ 10 : 8 ] 56h[7:0] the x location for reading ? pixel_out? register pixel_v 11 rw 5 7 h[ 10:8 ] 58h[7:0] the y location for reading ? pixel_out? register pixle_out 24 r 59h, 5ah, 5bh read out pixel located by ? pixel_h? and ? pixel_v? fc3_start 1 rw 5ch[ 4] forces auto calibration to recal culate h back porch channel_select 1 rw 5ch[3] only for single pixel input 0: takes input data from channel 1 1: takes input data from channel 0 dual_pixel 1 rw 5ch[2] 0: takes input data from one single channel 1: takes input data from both channels soft_start 1 rw 5ch[1] restarts auto calibration without going into reset ics_phase_state 1 rw 5ch[0] forces auto calibration to calculate the image quality for a particular clock phase when supplied by ics chips hsize_by842_en 1 rw 5dh[7] turn on internal hsize matching by8, 4, 2 when clock frequency calibration is done by8, 4, 2. used mainly for special non-full screen inputs. video_mode 1 rw 5dh[6] 0: disable input video mode 1: input is video input_yuv 1 rw 5dh[5] 0: input video format is rgb 1: input video format is yuv 4:2:2 yuv_signed 1 rw 5dh[4] 0: input video yuv format is unsigned 1: input video yuv format is signed decimation 1 rw 5dh[3] used when input resolution is higher than output 1: enable special decimation control 0: disable special decimation detect_en 2 rw 5dh[2:1] input data range detection. the results are put in register 64h and 65h 0: disable detection 1: detect max/min using r color 2: detect max/min using g color 3: detect max/min using b color agc_en 1 rw 5dh[0] automatic gain control enable agc_gain_red 8 rw 5eh gain amount for r color agc_gain_green 8 rw 5fh gain amount for g color agc_gain_blue 8 rw 60h gain amount for b color agc_offset_red 8 rw 61h offset amount for r color agc_offset_green 8 rw 62h offset amount for g color agc_offset_blue 8 rw 63h offset amount for b color input_max 8 r 64h detect ed maximum input data (please see 5dh) input_min 8 r 65h detected minimum input data (please see 5dh) ics_freq_state 1 rw 66h[5] forces auto calibration to calculate the hsize value for a particular clock frequency when supplied by ics chips ics_hsize_valid 1 rw 66h[4] indicates when hsize value is ready for cpu to read in ics mode. can be clear by cpu ics_iq_valid 1 rw 66h[3] ind icates when image quality is ready for cpu to read in ics mode. can be clear by cpu iq_valid 1 rw 66h[2] indicates when image quality is ready for cpu to read in regular non- ics mode. can be clear by cpu divisor_ valid 1 rw 66h[1] indicates when auto clock frequency calibration is done and frequency value is ready for cpu to read . can be clear by cpu
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 41 revision b non_full_screen 1 rw 66h[0] indicates when input data is non full screen. can be clear by cpu divisor_ value 11 r 67h[2:0], 68h read only register containing value of clock frequency when divisor_valid is asserted iq_value 30 r 69h[5:0], 6ah,6bh, 6ch read only register containing value of image quality when either ics_iq_valid or iq_valid is asserted panel_on 1 rw 6dh[0] 1: turn on all the outputs to the panel 0: disable outputs to the panel ( need to disable eeprom 265h[3], 26 6 h[7], 26 6 h[3], 26 7 h[7], 26 7 h[3] to get complete output disable). ics_hsize_value 11 r 6eh[2:0] , 6fh read only register containing value of hsize when ics_hsize_valid is asserted rom_ clk_sel 6 rw 70h[5:0] divisor value use to divide fast pwm_free_clk to slower free_clk 3.7. control flow when sd1 2 10 is powered up, the reference system and sd1 2 10 will perform the following functions in sequence: 1. system will generate a power-on reset to sd1 2 10 . 2. once the sd1 2 10 receives the reset, sd1 2 10 will load the contents of eeprom and start the auto-calibration process. 3. in the meantime, the external cpu can change the contents of the control registers of the sd1 2 10 . if necessary, the external cpu can send an additional reset to restart the whole process.
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 42 revision b 4. electrical specifications this section presents the electrical specifications of the sd1 2 10 . 4.1. absolute maximum ratings symbol parameter rating units vcc power supply -0.3 to 3.6 v vin input voltage -0.3 to vcc + 0.3 v vout output voltage -0.3 to vcc +0.3 v vcc5 power supply for 5v -0.3 to 6.0 v vin5 input voltage for 5v -0.3 to vcc5 + 0.3 v vout5 output voltage for 5v -0.3 to vcc5 +0.3 v tstg storage temperature -55 to 150 c 4.2. recommended operating conditions symbol parameter min. typ. max. units vcc power supply 3.0 3.3 3.6 v vin input voltage 0 vcc v vcc5 commercial power supply for 5v 4.75 5.0 5.25 v vin5 input voltage for 5v 0 - vcc5 v tj commercial junction operating temperature 0 25 115 c 4.3. general dc characteristics symbol parameter conditions min. typ. max. units iil input leakage current no pull ? up or pull - down -1 1 m a ioz tri-state leakage current -1 1 m a cin3 3.3v input capacitance 2.8 r f cout3 3.3v output capacitance 2.7 4.9 r f cbid3 3.3v bi-directional buffer capacitance 2.7 4.9 r f cin5 5v input capacitance 2.8 r f cout5 5v output capacitance 2.7 5.6 r f cbid5 5v bi-directional buffer capacitance 2.7 5.6 r f note: the capacitance above does not include pad capacitance and package capacitance. one can estimate pin capacitance by adding pad capacitance, which is about 0.5 r f, and the package capacitance
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 43 revision b 4.4. dc electrical characteristics for 3.3 v operation (under recommended operation conditions and v cc = 3.0 ~ 3.6v, t j = 0 c to +115 c) symbol parameter conditions min. typ. max. units vil input low voltage cmos 0.3*vcc v vih input high voltage cmos 0.7*vcc v vt- schmitt trigger negative going threshold voltage coms 1.20 v vt+ schmitt trigger positive going threshold voltage coms 2.10 v vol output low voltage ioh=2,4,8,12, 16,24 ma 0.4 v voh output high voltage ioh=2,4,8,12, 16,24 ma 2.4 v ri input pull-up /down resistance vil=0v or vih=vcc 75 k w 4.5. dc electrical characteristics for 5v operation (under recommended operation conditions and v cc =4.75~5.25,t j =0 c to +115 c) symbol parameter conditions min. typ. max. units vil input low voltage coms 0.3*vcc v vih input high voltage coms 0.7*vcc v vil input low voltage ttl 0.8 v vih input high voltage ttl 2.0 v vt- schmitt trigger negative going threshold voltage cmos 1.78 v vt+ schmitt trigger positive going threshold voltage coms 3. 00 v vt- schmitt trigger negative going threshold voltage ttl 1.10 v vt+ schmitt trigger positive going threshold voltage ttl 1.90 v vol output low voltage iol=2,4,8,16,24ma 0.4 v voh output high voltage ioh=2,4,8,16,24 ma 3.5 v ri input pull-up / down resistance vil=0v or vih=vcc 50 k w
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 44 revision b 5. package dimensions d q l l1 1 40 80 120 160 160 pqfp (28x28 mm) c e a1 a2 a b hd he e
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 45 revision b symbol\unit inch (base) mm (base) a 0.154 (min) ? 0.160(max) 3.92 (min) ? 4.06 (max) a1 0.010 (min) 0.25 (min) a2 0.127 +/-0.003 3.22 +/- 0.08 b 0.010 (min) ? 0.014(max) 0.25(min) ? 0.35(max) c .005 (min) ? 0.009 (max) 0.13(min) ? 0.25(max) d 1.102+/-0.002 28.000+/-0.10 e 1.102+/-0.002 28.000+/-0.10 e 0.026 (ref) 0.65 (ref) hd 1.228 +/- 0.01 31.20 +/- 0.25 he 1.228 +/- 0.01 31.20 +/- 0.25 l 0.031+/-0.006 0.80+/-0.15 l1 0.063(ref) 1.60(ref) q 0 - 7.0 0 - 7.0
smartasic, inc. sd1 2 10 novembe r , 1999 smartasic confidential 46 revision b 6. order information order code temperature package speed sd1 2 10 commercial 0 c ~ 70 c 160-pin pqfp 28 x 28 (mm) 100mhz smartasic, inc . worldwide offices u.s.a. & europe asia pacific 525 race st. suite 250 3f, no. 68, chou- tze st. nei-hu dist. san jose, ca 951 26 u.s.a. taipei 114 , taiwan r.o.c. tel : 1-408- 283-5098 tel : 886-2- 8797-7889 fax : 1-408- 283-5099 fax : 886-2- 8797-6829 @copyright 1999, smartasic, inc. this information in this document is subject to change without notice. smartasic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. smartasic does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.

▲Up To Search▲

Price & Availability of SD1210

	To Download SD1210 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .